This invention relates to the field of non-volatile semiconductor memory devices. More particularly, this invention relates to an improved non-volatile semiconductor memory device of the insulated gate field effect transistor (IGFET) type and a method of fabricating same.
Non-volatile semiconductor memory devices are known which typically employ a large scale integration (LSI) array of individual non-volatile IGFET elements with suitable interconnections to function as a multibit storage device, such as a read only memory (ROM), a read mostly memory (RMM), an electronically alterable read only memory (EAROM), a random access memory (RAM) or the like. Each non-volatile IGFET element typically comprises a semiconductor substrate material of a first conductivity type, a pair of source and drain diffusion regions of opposite conductivity type from the substrate material and separated by an interstitial portion of the substrate material, an overlying dielectric oxide layer of minimum thickness in the region overlying the interstitial substrate portion, a layer of a different dielectric material over the oxide layer and a gate electrode metallization layer overlying the dielectric material. In addition, an ohmic contact is provided for each diffusion region so that supply voltages may be coupled thereto from suitable sources. The non-volatile IGFET element can be operated as a two-state memory device by virtue of the variable threshold switching property exhibited by devices of this type. In a conventional field effect transistor, the threshold voltage which must be applied between the gate and the source electrodes to cause current conduction between the drain and the source electrodes is fixed. In non-volatile IGFET devices, on the other hand, this threshold voltage can be altered by applying a relatively large potential difference between the gate electrode and the substrate. The threshold voltage may be altered back to an initial level by applying a relatively large potential difference of opposite polarity between the gate and the substrate. If the two different threshold voltages are well defined and of sufficiently different magnitude, a non-volatile IGFET may be operated as a bistable memory device by arbitrarily assigning one and zero values to the different threshold voltages, selectively altering the threshold voltage and subsequently interrogating the IGFET with a voltage whose magnitude lies between the two different threshold voltages while sensing the source-to-drain current. Circuits have been designed employing non-volatile IGFET as bistable memory elements, and several representative circuits are shown in U.S. Pat. No. 3,636,530.
Metal-nitride-oxide-silicon (MNOS) IGFET memory devices using silicon nitride as the dielectric element have been fabricated for use as bistable memory elements and, while MNOS implementation has many advantages, the performance of such devices has not been found to be entirely satisfactory. One of the chief reasons for the unsatisfactory performance to date of variable threshold IGFET memory devices is the lack of predictability of the two different threshold voltages noted above. In the ideal case, the gate voltage-drain current characteristic of the device would consist of a pair of highly linear curves with very steep slopes and separated by a sufficient range of voltage so that a range of gate voltages would exist which would cause the device to conduct heavily only if the device had been previously placed in the lower voltage threshold. Conventional prior art devices do not approach the ideal case, however, and exhibit parasitic effects which result in gate voltage-drain current characteristics which vary between individual elements on a LSI chip and also vary from chip to chip in an unpredictable manner. Due to this unpredictability, it is difficult to assign a priori a range of interrogating gate voltages which will result in conduction only when the MNOS device is in one of the two variable threshold states. Further, the nature of these parasitic gate voltage-drain current characteristics is such that in either state the device may conduct heavily by applying the same interrogating gate voltage of a given magnitude. Stated differently, interrogation of a prior art variable threshold IGFET device having parasitic characteristics with a gate voltage of a given magnitude does not cause the device to conduct heavily only in one state.
The apparent reason for this parasitic behavior of conventional devices appears to reside in the geometry required to produce an operable non-volatile IGFET device. As noted above, such a device has an overlying oxide layer of minimum thickness in the region overlying an interstitial exposed portion of the substrate material which separates the two different regions, with the oxide being covered by a layer of different dielectric material which in turn is covered by a metallization layer. The field oxide layer elsewhere has a substantially uniform thickness many orders of magnitude greater than the minimum thickness. Between the thick oxide region and the thin oxide region their exists a transition sometimes termed a "sidewalk" which functions as an MNOS device with gradually increasing oxide thickness. When the MNOS memory region is switched between high and low threshold voltages, this transition region is switched to a threshold voltage somewhere between the high and low values of the main memory region. Thus, when the main channel is set at high threshold voltage, this transition region may be conducting at voltages lying below the high threshold voltage. Schematically, the equivalent device would comprise a single MNOS memory element and two flanking MOS devices with the source, drain and gate elements coupled in parallel.
Many efforts have been made to solve this parasitic problem. One such attempt has been to broaden the gate region in a direction perpendicular to the line separating the diffusion regions so that the thin oxide gate region extends beyond the overlying gate electrode metallization layer. This solution introduces an additional problem due to the fringing electric field from the gate, termed the floating gate problem, in which charges tend to accummulate around the edge of the nitride insulation overlying the gate region, with the result that the device rapidly degenerates into a different type of parasitic device exhibiting substantially the same parasitic behavior as that noted above.
Another proposed solution has been the provision of a heavy ion implantation region in the gate region which extends beyond the edges of the overlying gate electrode metallization layer in the direction noted above. While this solution has been found to raise the threshold voltage of the regions adjacent the gate metallization layer beyond the high threshold voltage of the variable threshold IGFET device, the ion implantation step is relatively difficult to perform in a controlled manner and inordinately lengthens the manufacturing process. An alternate variation of this solution has been the provision of a pair of independent blocking diffusion regions extending beyond opposite edges of the gate electrode metallization layer in the direction noted above and also partially into the gate region. This alternate solution, however, suffers from the same limitations as those noted above in that it requires additional processing steps which increase the cost of manufacturing devices of this type. Accordingly, efforts to date to provide a variable threshold IGFET memory device in LSI form substantially free of the parasitic effects noted above have not met with wide success.